| Jiahui's Personal Website |
About me:
Hi! I am Jiahui Xu, a PhD student from Beijing, China. I joined the Digital Systems and Design Automation Group (DYNAMO) at ETH Zurich in 2022. I am supervised by Prof. Lana Josipović. My research aims to improve the quality and reliability of high-level synthesis (HLS) design flow using formal methods. Currently, I am focusing on various aspects of using model checking to alleviate the resource overhead of dynamically-scheduled circuits produced from HLS.
I have a background in telecommunications engineering. I hold a bachelor's degree in Electronic and Communications engineering from Politecnico di Torino, and a master’s degree in Communications Engineering from the Technical University of Munich.
| Education |
| Ph.D., ETH Zurich (2022–Present) in the Dept. of Information Technology and Electrical Engineering. |
| M.Sc. with high distinction, Technical University of Munich (2019–2021) in Communications Engineering. |
| B.Sc., Politecnico di Torino (2016–2019) in Electronic and Communications Engineering. |
| Awards |
| MSCE Academic Award in 2021 (with M.Sc. in Communications Engineering). |
| Academic Services |
| Publicity co-chair at IWLS ('24, '25). |
| Reviewer for TCAD ('24). |
| Secondary reviewer at ASAP ('23), DSD ('23), FPT ('22, '23), FPGA ('24). |
| Artifact evaluator at FPGA ('24). |
| Publications |
Checkout also my Google Scholar profile.
| Ayatallah Elakhras*, Jiahui Xu*, Martin Erhart, Paolo Ienne, and Lana Josipović. ElasticMiter: Formally Verified Dataflow Circuit Rewrites. In Proceedings of the 30th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '25), to appear, Rotterdam, The Netherlands, March 2025. *Equal contributions. |
| Jiahui Xu and Lana Josipović. CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS. In Proceedings of the 30th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '25), to appear, Rotterdam, The Netherlands, March 2025. [paper] [code] |
| Jiahui Xu and Lana Josipović. CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS. In Proceedings of the 33rd International Workshop on Logic and Synthesis (IWLS '24), Zurich, Switzerland, June 2024. |
| Jiahui Xu and Lana Josipović. Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. In Proceedings of the 32nd ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '24), pages 188–98, Monterey, CA, March 2024. [paper] [code] |
| Jiahui Xu and Lana Josipović. Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. In Proceedings of the International Conference on Computer-Aided Design (ICCAD '23), pages 1–9, San Francisco, CA, October 2023.[paper] [code] |
| Jiahui Xu and Lana Josipović. Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. In Proceedings of 32nd International Workshop on Logic and Synthesis (IWLS '23), pages 179–87, Lausanne, June 2023. |
| Jiahui Xu, Emmet Murphy, Jordi Cortadella, and Lana Josipović. Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In Proceedings of the 31st ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '23), pages 27–37, Monterey, CA, February 2023. [paper] [code] |